This application claims benefit of Japanese Patent Application No. 2000-005785 filed on Jan. 6, 2000, the contents of which are incorporated by the reference.
The present invention relates to clock generators and, more particularly, to clock generators for reference clock generation in digital portable telephone terminals or the like.
Portable telephone or like radio communication terminals require an accurate and highly stable clock as a reference of operation of their component circuits. Such a portable telephone terminal has a circuit for controlling the frequency of an oscillator (for instance crystal oscillator) of its own clock generator to match received wave from a base station. This circuit is well known as AFC (Automatic Frequency Control) circuit. Prior art examples of the AFC circuits are disclosed in, for instance, Japanese Patent Laid-Open No. 9-199997 and Japanese Patent Laid-Open No. 10-284997. Prior art example of the receiver using such a clock generator is disclosed in, for instance, Japanese Patent Laid-Open No. 7-202737. Prior art example of the PLL (Phase Locked Loop) is disclosed in, for instance, Japanese Patent Laid-Open No. 8-251019.
A multi-system terminal or the like employing a system using a clock controlled by an AFC circuit (hereinafter referred to as main system), also employs a coexistent system utilizing the frequency of a crystal oscillator or the like (hereinafter referred to as sub-system). FIG. 6 shows an example of such terminal. As shown, the terminal comprises a main system 611 and a sub-system 612 receiving a system clock supplied therefrom. The main system 611 is a current PDC or a next era WCDMA system for portable terminal (i.e., portable telephone terminal). Alternatively, the main system 611 may be PHS (Personal Handy phone System). The sub-system 612 is subordinate to such main system and may, for instance, be a blue tooth system.
In the portable telephone terminal, the reference clock generator should be very highly accurate. As reference clock generator, usually a TCXO (temperature compensated crystal oscillator) is used. In the multi-system, the use of a TCXO in each system is undesired, and particularly disadvantageous in portable remote terminals which are demanded to be small in size and light in weight, because of increase of components. Accordingly, as shown in the block diagram of FIG. 7, a TCXO 70 is provided in the sole main system, and its output clock is used in the plurality of PLL circuits, i.e., a radio terminal side PLL circuit (first PLL circuit) 71, a control circuit clock generator 72 (second PLL circuit) for main system control PLL and a blue tooth clock generator (third PLL circuit) 73 for sub-system ratio or control part PLL.
FIG. 8 is a block diagram showing a general PLL circuit. This circuit comprises a TCXO 80, an AFC circuit 81, a frequency divider A82, registers 83, 86 and 89, a phase comparator 84, a charge pump 85, a VCO (Voltage Controlled Oscillator) 87 and a frequency divider B 88. The registers 83 and 89 control the frequency division ratios of the frequency dividers A82 and B82, respectively. The register 86 controls the phase compensator 84 and the charge pump 85. The circuit having this PLL construction operates such that the value obtained by the division of the output frequency fr of the TCXO 80 by the frequency division ratio Da of the frequency divider A82 becomes equal to the value obtained by the division of the output frequency fo of the VCO 87 by the frequency division ratio Db of the frequency divider B 88. That is,
fr/Da=fo/Db xe2x80x83xe2x80x83(1). 
The equation (1) can be changed to the following equation (2).
fo=frxDa/Db xe2x80x83xe2x80x83(2). 
As a result, the output of the VCO 87 is determined by multiplying the output frequency of TCXO 80 with division ratios of the both frequency divider 82 and 88. An output at a desired frequency thus can be obtained by varying the frequency division ratios with the registers 83 and 89.
The general AFC function of, for instance, a portable telephone terminal will now be described with reference to FIG. 9. The function is to synchronize the terminal to received wave from a BTS (Base Transcriber Station). The system shown in FIG. 9 comprises a BTS 90 having an antenna 91, an antenna 92, a radio circuit 93, an AFC circuit 94 including an adder/average error calculator circuit 95 and a D/A (digital-to-analog) circuit 96 and a TCXO 97.
The received wave from the BTS 90 varies instantaneously due to such cause as fading in the propagation path. The AFC circuit 94 is adapted to provide synchronization to the received wave even in such a case. The radio unit 93 demodulates the high frequency wave received from the BTS 90 to provide a base band output. The adder/average error calculator circuit 95 in the AFC circuit 94 calculates a phase error, and the D/A converter 96 D/A converts the phase error and feeds out the resultant analog voltage to the TCXO 97.
In the system shown in FIG. 7, the clock of the sub-system (Blue Tooth) PLL should not be subject to variation. However, as disclosed the foregoing, the reference frequency change of the TCXO 80 by the AFC circuit 81 causes the corresponding change in the output frequency of the VCO 87. As noted above, the frequency variations are undesired in the sub-system (because of resultant adverse effects on the circuit operation, and the sub-system is desired to use a clock free from the influence of the AFC function, which is used in the main system, for instance.
The present invention accordingly has an object of providing a clock generator, which is used for a system having a main system and a sub-system and permits the sub-system to generate a clock free from the influence of AFC function used in the main system.
According to an aspect of the present invention, there is provided a clock generator for a multi-system comprising a TCXO (temperature compensated crystal oscillator) controlled by an AFC (automatic frequency control) circuit and a sub-system operative with a system clock supplied from the main system and including a PLL (phase locked loop) circuit having a phase comparator and a VCO (voltage controlled oscillator), wherein: the frequency division ratio of a frequency divider in the PLL circuit is compensated on the basis of the output of the AFC circuit to absorb phase changes due to the AFC circuit.
The frequency divider in the PLL circuit controlled by the AFC circuit is a first frequency divider for frequency dividing the output of the TCXO. The frequency divider in the PLL circuit controlled by the AFC circuit is a second frequency divider for frequency dividing the output of the VCO. The clock generator further comprises a register for changing the frequency division ratio of the frequency divider according to phase changes in the AFC circuit. The clock generator further comprises a temperature sensor for detecting the temperature of the TCXO and a memory for storing detected temperature data obtained in the temperature sensor and characteristic change data of the TCXO, data stored in the memory being referred to at the time of the frequency division ratio compensation on the basis of the output of the AFC circuit. The clock generator further comprises a charge pump including a pulse waveform compensating circuit provided at the preceding stage to the VCO.
According to another aspect of the present invention, there is provided a clock generator comprising a TCXO (temperature compensated crystal oscillator) controlled by an AFC (automatic frequency control) circuit, a first frequency divider for frequency dividing the output of the TCXO, a phase comparator for receiving the output of the first frequency divider as one input, a charge pump for receiving the output of the phase comparator, a VCO (voltage controlled oscillator) for feeding out an oscillation frequency according to the output voltage of the charge pump, a second frequency divider for frequency dividing the output of the VCXO and feeding out the result of the frequency division as the other input to the phase comparator, and a temperature sensor for detecting the temperature of the TCXO, the AFC circuit executing control of the TCXO on the basis of the detected temperature in the temperature sensor and frequency change data of the TCXO.
According to other aspect of the present invention, there is provided a digital portable terminal or a portable telephone terminal including the clock generator defined in the foregoing.
The clock generator according to the present invention finds application to a terminal having two coexistent systems, i.e., a main system and a sub-system (hereinafter referred to as multi-system), in which the system clock of the sub-system is generated with reference to the system clock of the main system, and has an effect that a stable system clock can be supplied to the sub-system canceling system clock changes which may occur due to the main system AFC function.
Other objects and features will be clarified from the following description with reference to attached drawings.